1. Field of the Invention
The present invention relates to a semiconductor device, a method for producing a semiconductor device, and a method for producing an interposer substrate. More particularly, the present invention relates to a BGA type semiconductor.
2. Description of the Related Art
A BGA (Ball Grid Array) type semiconductor package has conventionally been proposed, wherein solder bumps serving as external terminals are arranged in a matrix on a back surface of a package, on which a semiconductor chip is mounted. When compared, for example, with a QFP (Quad Flat Package) type semiconductor package where external terminals are arranged around the package, the BGA type semiconductor package can increase a number of the terminals without decreasing the size thereof, thereby contributing to reduce a size of an electronic device.
FIG. 13 shows an example of a conventional BGA type semiconductor package. The semiconductor package 100 shown in FIG. 13 includes an insulating layer 104 made of polyimide, or the like, formed on a base metal substrate 102, and a fine copper wiring 106 is formed on the insulating layer 104. The base metal substrate 102 serves as a ground layer and a heat sink for dissipating heat. A semiconductor chip 108 is adhered to a depression at a center of the package with an adhesive 110 such as a die bonding material. Electrodes on the semiconductor chip 108 are connected to predetermined sites of the copper wiring 106 by wire bonding via wires 112. Solder balls 114 are formed at predetermined sites of the copper wiring 106. The semiconductor chip 108 is sealed by a sealing resin 116.
In the semiconductor package having the above-described structure, there is one wiring layer and a distance between the base metal substrate 102 serving as the ground layer and each site of the copper wiring 106 is substantially the same. Therefore, the semiconductor package having the above-described structure has better electric characteristics and can be produced at a lower cost than a semiconductor package having a multi-layer wiring structure.
Further, a semiconductor device having a structure shown in FIG. 14 is proposed in Japanese Patent Application Laid-Open (JP-A) No. 11-330301. The semiconductor device 200 shown in FIG. 14 includes a semiconductor chip 120 mounted at a center of a wiring resin substrate 118 with a circuit-forming surface of the chip facing away from the wiring resin substrate 118. A top surface of the semiconductor chip 120 is fixed to a heat sink 122 with an adhesive. A conducting portion 124 made of a metal foil is formed on a top surface of the wiring resin substrate 118. Metal foil wiring, which includes pads 126 and inner leads 128, is formed on a bottom surface of the wiring resin substrate 118. The conducting portion 124 is connected to the pads 126 through via holes 130. Tips of the inner leads 128 are connected to bumps 132 serving as electrodes formed on the semiconductor chip 120 by so-called ILB (Inner Lead Bonding). The circuit-forming surface and portions of side surfaces of the semiconductor chip 120, the inner leads 128, and portions of the wiring resin substrate 118 are sealed with a resin 134. Thus, the semiconductor device 200 has a so-called TAB (Tape Automated Bonding) structure.
Furthermore, a semiconductor device 300 having a structure shown in FIG. 15 is proposed in JP-A No. 2000-31323. The semiconductor device 300 shown in FIG. 15 includes a metal plate layer 138 fixed on a heat sink 136 with an adhesive 140. An IC chip 142 is disposed at a center of the metal plate layer 138. A plastic layer 144 is laminated on the metal plate layer 138. A wiring pattern 146 and solder holes 148 are formed on the plastic layer 144. Electrodes provided on a top surface of the IC chip 142 are connected to the wiring pattern 146 by wire bonding via Au leads 150. The electrodes and an upper portion of the wiring pattern 146 are sealed with a sealing resin 152.
However, in the semiconductor package having the structure shown in FIG. 13, bottom surfaces of the solder balls 114 are positioned lower than a lower end of the sealing resin 116, and therefore, a portion of the substrate where the semiconductor chip 108 is mounted has to be formed as a depression by molding using a metal mold, or the like. This leads to an increase in production costs of the semiconductor package. Moreover, since a difference in level is formed at a surface of the semiconductor package 100, if an additional heat sink for dissipating heat is mounted, the heat sink has to be made in a special shape which fits the shape of the semiconductor package 100 having the difference in level, and this may lower a yield of the semiconductor package.
Further, since the semiconductor device having the structure shown in FIG. 14 described in JP-A No. 11-330301 has the TAB structure, it is necessary to form bumps on the semiconductor chip 120, and this increases production costs.
Moreover, in the semiconductor device having the structure shown in FIG. 15 described in JP-A No. 2000-31323, since wire bonding is performed on the wiring pattern 146 formed on the surface which is the same surface as where the solder balls 148 are formed, heights of the Au leads 150 are restricted by heights of the solder balls 148. Therefore, it is difficult to employ double wire bonding, which is employed for semiconductor devices having a large number of electrode pads such as an ASIC, and therefore it is difficult to increase a number of terminals and a degree of freedom in designing this semiconductor device is limited.